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?1 CXA2040Q e95z44-st i 2 c bus-compatible video switch description the CXA2040Q is an i 2 c bus-compatible 5-input, 3-output video switch for tvs. features serial data control via i 2 c bus 5 composite video input systems 2 y/c (s terminal) input systems 3 composite video output systems 1 y/c (s terminal) output system input can be selected independently for each output system. sync_id function for cv1 system input built-in 6db amplifier for cvout2 system output built-in y/c mix circuit slave address can be changed (90h/92h). high impedance maintained by i 2 c bus line (sda, scl) even when power is off. applications tvs pin configuration (top view) absolute maximum ratings (ta = 25?) supply voltage v cc 12 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 1.0 w (when mounted on a 50mm 50mm board) operating conditions supply voltage v cc 9.0 0.5 v structure bipolar silicon monolithic ic sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 32 pin qfp (plastic) nc cv1 synctc sda scl adr nc cvout1 17 18 19 20 21 22 23 24 nc cvout2 nc cvout3 nc yout nc cout 9 10 11 12 13 14 15 16 y1 nc c1 s1 y2 s2 c2 nc 2 3 4 5 6 7 8 1 bias cv2 v cc cv3 nc cv4 gnd cv5 26 27 28 29 30 31 32 25
?2 CXA2040Q block diagram s2 cvout1 adr scl sda cvout2 cvout3 yout cout sw1 sw2 sw3 i 2 c bus decoder cv1 cv2 cv4 cv6 mute cv3 cv5 cv7 cv1 cv2 cv4 cv6 mute cv3 cv5 cv7 cv1 cv2 cv4 cv6 mute cv3 cv5 cv7 cv7 cv6 cv5 cv4 cv3 cv2 cv1 mute sync detect mute c2 c1 sw5 bias mute y2 y1 sw4 6 s1 4 19 20 21 cv2 cv3 cv4 cv5 bias synctc cv1 22 23 32 c2 y2 c1 y1 7 17 9 11 13 15 5 3 1 27 29 31 25 6db 26 30 v cc gnd * numbers inside circles indicate the ic pin numbers.
?3 CXA2040Q pin description pin no. symbol pin voltage equivalent circuit description 1 5 3 7 y1 y2 c1 c2 4.5v y/c separation signal inputs. biased to approximately 4.5v. input the input signals through capacitors. connect protective resistor of 220 between these pins and the capacitors. y1 and y2 pins: luminance signals input. c1 and c2 pins: chrominance signals input. 4 6 s1 s2 applying a dc voltage to s1 and s2 pins allows these voltages to be applied to the microcomputer as the i 2 c bus status register data. s1, s2 = 0 to 2v open = 0, sel = 1 s1, s2 = 4.75 to 7.25v open = 0, sel = 0 s1, s2 = 9.5 to 12v open = 1, sel = 0 11 9 yout cout 4.5v y/c signal outputs. yout pin: luminance signal output. cout pin: chrominance signal output. 17 15 13 cvout1 cvout2 cvout3 4.5v composite video signal outputs. cvout1, cvout2: 0db output with respect to the input signal. cvout2: +6db output with respect to the input signal. 5 7 1 20k 147 28k v cc 2 3 6 50k 100k v cc 50k 4 4 v cc 2 200 1.2k 2 5 6 9 11 v cc 2 200 1.2k 2 5 6 13 15 17
?4 CXA2040Q 19 adr selects the slave address for the i 2 c bus. 90h at 1.0v or less 92h at 3.5v or more 90h when open 20 scl i 2 c bus signal input. connect protective resistor of 220 between this pin and the scl line. 21 sda i 2 c bus signal input. connect protective resistor of 220 between this pin and the sda line. 22 synctc sync tip clamp time constant for sync separation. connect 68k resistor between this pin and v cc . connect 10f capacitor between this pin and gnd. 19 72k 28k v cc 20 4k 4 v cc 21 4k 6 v cc 1.2k v cc 22 147 147 1.2k pin no. symbol pin voltage equivalent circuit description
?5 CXA2040Q 23 cv1 4.5v composite video signal input. biased to approximately 4.5v. input the input signal through capacitor. connect protective resistor of 220 between this pin and the capacitor. the composite video signal input to cv1 is also taken into the "sync detect circuit" of which sync is existed or not. 25 27 29 31 cv2 cv3 cv4 cv5 4.5v composite video signal input. biased to approximately 4.5v. input the input signals through capacitors. connect protective resistor of 220 between these pins and the capacitors. 26 v cc 9.0v * 1 power supply. apply 9.0v. 30 gnd 0.0v * 1 gnd. 32 2 8 10 12 14 16 18 24 28 bias nc 4.5v 4.5v bias. attach a decoupling capacitor between this pin and gnd. this pin cannot be used as an external power supply. nc (not connected). connect to gnd. if these nc pins are not connected to gnd, the cross talk and other desired values indicated in the electrical characteristics cannot be obtained. 23 20k 147 28k v cc 20k 147 28k v cc 25 27 29 31 20k v cc 32 22.5k 1.2k * 1 applied externally. pin no. symbol pin voltage equivalent circuit description
?6 CXA2040Q measure the pin inflow current. measure the pin voltage. 20log 20log 20log * since the sum of 0.15vp-p and 0.15vp-p is input to each switch, calculations are performed with 0.3vp-p. no. item symbol measurement conditions v cc = 9v, no signal v cc = 9v, no signal cv1 in, cv2 in, cv3 in, cv4 in or cv5 in 100khz, 0.3vp-p cw select each input with i 2 c bus control and obtain the i/o gain. cv1 in, cv2 in, cv3 in, cv4 in or cv5 in 100khz, 0.3vp-p cw select each input with i 2 c bus control and obtain the i/o gain. y1 and c1 (cv6) in or y2 and c2 (cv7) in 100khz, 0.15vp-p cw select each input with i 2 c bus control and obtain the i/o gain. 26 32 13, 17 15 13, 17 18.0 4.25 ?.40 5.75 ?.40 27.7 4.50 0.00 6.25 0.10 39.0 4.75 0.40 6.75 0.60 ma v db db db 1 2 3 4 5 current consumption pin voltage cv system gain 1 cv system gain 2 cv system (y/c mix) gain 1 i cc v bias g cv11 g cv21 g cvm11 measurement pins measurement contents min. typ. max. unit v cv11 v cv21 v cvm11 v cv11 0.3vp-p v cv21 0.3vp-p v cvm11 0.3vp-p electrical characteristics see electrical characteristics measurement circuit 2 for cross talk and mute. (ta = 25?, v cc = 9v) see electrical characteristics measurement circuit 1 for all other items.
?7 CXA2040Q 20log * since the sum of 0.15vp-p and 0.15vp-p is input to each switch, calculations are performed with 0.3vp-p. 20log 20log 20log * v cv11 and v cv12 should be the same i/o. y1 and c1 (cv6) in or y2 and c2 (cv7) in 100khz, 0.15vp-p cw select each input with i 2 c bus control and obtain the i/o gain. y1 in or y2 in 100khz, 0.3vp-p cw select each input with i 2 c bus control and obtain the i/o gain. c1 in or c2 in 100khz, 0.3vp-p cw select each input with i 2 c bus control and obtain the i/o gain. cv1 in, cv2 in, cv3 in, cv4 in or cv5 in 10mhz, 0.3vp-p cw select each input with i 2 c bus control and obtain the i/o gain. then obtain the difference from the i/o gain measured by test 3. 15 11 9 13, 17 5.75 ?.40 ?.40 ?.85 6.40 0.00 0.00 ?.15 7.05 0.40 0.40 0.55 db db db db 6 7 8 9 cv system (y/c mix) gain 2 y system gain c system gain cv system frequency response 1 g cvm21 g y11 g c11 ? g cv12 v cvm21 v y11 v c11 v cv12 v cvm21 0.3vp-p v y11 0.3vp-p v c11 0.3vp-p v cv12 v cv11 no. item symbol measurement conditions measurement pins measurement contents min. typ. max. unit
?8 CXA2040Q 20log * v cv21 and v cv22 should be the same i/o. 20log * v cvm11 and v cvm12 should be the same i/o. 20log * v cvm21 and v cvm22 should be the same input. 20log * v y11 and v y12 should be the same input. cv1 in, cv2 in, cv3 in, cv4 in or cv5 in 10mhz, 0.3vp-p cw select each input with i 2 c bus control and obtain the i/o gain. then obtain the difference from the i/o gain measured by test 4. y1 and c1 (cv6) in or y2 and c2 (cv7) in 10mhz, 0.15vp-p cw select each input with i 2 c bus control and obtain the i/o gain. then obtain the difference from the i/o gain measured by test 5. y1 and c1 (cv6) in or y2 and c2 (cv7) in 10mhz, 0.15vp-p cw select each input with i 2 c bus control and obtain the i/o gain. then obtain the difference from the i/o gain measured by test 6. y1 in or y2 in 10mhz, 0.3vp-p cw select each input with i 2 c bus control and obtain the i/o gain. then obtain the difference from the i/o gain measured by test 7. 15 13, 17 15 11 ?.85 ?.75 ?.75 ?.70 ?.15 ?.25 ?.25 0.00 0.55 1.25 1.25 0.70 db db db db 10 11 12 13 cv system frequency response 2 cv system (y/c mix) frequency response 1 cv system (y/c mix) frequency response 2 y system frequency response ? g cv22 ? g cvm12 ? g cvm22 ? g y12 v cv22 v cv21 v cvm12 v cvm11 v cvm22 v cvm21 v y12 v y11 v cv22 v cvm12 v cvm22 v y12 no. item symbol measurement conditions measurement pins measurement contents min. typ. max. unit
?9 CXA2040Q the input waveform amplitude value when pins 13, 15 or 17 output waveform distortion factor = 1%. y1 or y2 input waveform the input waveform amplitude value when pins 13, 15 or 17 output waveform distortion factor = 1%. c1 or c2 input waveform the input waveform amplitude value when pins 13, 15 or 17 output waveform distortion factor = 1%. the input waveform amplitude value when pin 11 output waveform distortion factor = 1%. the input waveform amplitude value when pin 9 output waveform distortion factor = 1%. cv1 in, cv2 in, cv3 in, cv4 in or cv5 in f = 100khz cw select each input with i 2 c bus control and then increase the input waveform amplitude. y1 (cv6) in or y2 (cv7) in f = 100khz cw select each input with i 2 c bus control and then increase the input waveform amplitude. c1 (cv6) in or c2 (cv7) in f = 100khz cw select each input with i 2 c bus control and then increase the input waveform amplitude. y1 in or y2 in f = 100khz cw select each input with i 2 c bus control and then increase the input waveform amplitude. c1 in or c2 in f = 100 khz cw select each input with i 2 c bus control and then increase the input waveform amplitude. 23, 25, 27, 29, 31 1, 5 3, 7 1, 5 3, 7 2.2 2.2 0.95 2.2 2.2 vp-p vp-p vp-p vp-p vp-p 14 15 16 17 cv system input dynamic range cv system (y/c mix) input dynamic range y system input dynamic range c system input dynamic range v cv13 v cvmy33 v cvmc33 v y13 v c13 v cv13 the value for the pal composite signal should correspond to an amplitude of approximately 1vp-p + 3db. the value for the pal y signal should correspond to an amplitude of approximately 1vp-p + 3db. the value for the pal c signal should correspond to an amplitude of approximately 0.66vp-p + 3db. v cvmy v cvmc v y13 v c13 the value for the pal y signal should correspond to an amplitude of approximately 1vp-p + 3db. the value for the c signal should correspond to an amplitude of approximately 2.2vp-p. no. item symbol measurement conditions measurement pins measurement contents min. typ. max. unit
?10 CXA2040Q cross talk mute cv system 1, y system, c system mute (cv system 2) select the input with i 2 c bus control and ground that input pin via a capacitor. input a 4.43mhz, 1vp-p cw to one input pin system among the remaining 8 input pins (7 input pins for y/c mix). then ground the remaining 7 input pins (6 input pins for y/c mix) via capacitors. set this pin to mute status with i 2 c bus control and input a 4.43mhz, 1vp-p cw to one input pin system. then ground the remaining 8 input pins via capacitors. set this pin to mute status with i 2 c bus control and input a 4.43mhz, 1vp-p cw to one input pin system. then ground the remaining 8 input pins via capacitors. 9, 11, 13, 15, 17 9, 11, 13, 17 15 read the output waveform value. 20log read the output waveform value. 20log read the output waveform value. 20log ?5 ?0 ?5 db db db 18 19 20 g crs g m1 g m2 v x v x 1vp-p v x 1vp-p v x 1vp-p v x v x no. item symbol measurement conditions measurement pins measurement contents min. typ. max. unit
?11 CXA2040Q cv1 in: sig-1 cv1 in: sig-2 cv1 in: sig-3 cv1 in: sig-4 21 (sda) 21 (sda) 21 (sda) 21 (sda) input sig-1 to cv1 and check that bit 5 "syncsep" of the i 2 c bus status register is "1" when the sig-1 sync level is 100mv or more. input sig-2 to cv1 and check that bit 5 "syncsep" of the i 2 c bus status register is "0" when the sig-2 sync level is 30mv or less. input sig-3 to cv1 and check that bit 5 "syncsep" of the i 2 c bus status register is "1" when the sig-3 duty is 91% or more (the sync width is 5.72s or less). input sig-4 to cv1 and check that bit 5 "syncsep" of the i 2 c bus status register is "0" when the sig-4 duty is 84% or less (the sync width is 10.17s or more). the sig-1 sync level should correspond to approximately ?db when the 1vp-p ntsc composite signal sync level (286mv) is set as 0db. the sig-2 sync level should correspond to approximately ?9db when the 1vp-p ntsc composite signal sync level (286mv) is set as 0db. sync is determined to exist when the sync level is 100mv or more and a rectangular wave with a duty of 91% or more is input to cv1. sync is determined not to exist when a rectangular wave with a duty of 84% or less is input to cv1 even when the sync level is 100mv or more. 21 22 23 24 sync discrimination 11 sync discrimination 21 sync discrimination 12 sync discrimination 22 syncd11 syncd21 syncd12 syncd22 100 mv 63.56s 4.70s 100mv 63.56s 4.70s 30mv 63.56s 5.72s 286mv duty = 91% 63.56s 10.17s 286mv duty = 84% 30 mv 91 % 84 % no. item symbol measurement conditions measurement pins measurement contents min. typ. max. unit
?12 CXA2040Q vary the pin 19 v adr . 21 the slave address goes to 92h at high level and 90h at low level. 25 adr threshold voltage v adr v th 1.0 3.5 v no. item symbol measurement conditions measurement pins measurement contents min. typ. max. unit
?13 CXA2040Q electrical characteristics measurement circuit 1 bias cv2 v cc cv3 nc cv4 gnd cv5 nc cvout2 nc cvout3 nc yout nc cout nc cv1 synctc sda scl adr nc cvout1 y1 nc c1 s1 y2 s2 c2 nc c2 2.2 y2 2.2 c1 2.2 y1 2.2 vs1 vs2 0.47 10k 10 10k 10 10k 10 10k cv1 68k v adr 0.1 i 2 c bus i/o 17 18 19 20 21 22 23 24 cv2 2.2 v cc 9v cv3 2.2 cv4 2.2 cv5 2.2 33 0.01 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 1 26 27 28 29 30 31 32 25 10 10k 2.2 * 1 unless otherwise specified in the measurement conditions column of electrical characteristics, all are gnd. * 2 unless otherwise specified in the measurement conditions column of electrical characteristics, the supply voltages are as follows. v cc = 9v, v s1 = 0v, v s2 = 0v v adr = 0v when operated with a slave address of 90h. v adr = 9v (v cc ) when operated with a slave address of 92h.
?14 CXA2040Q electrical characteristics measurement circuit 2 (cross talk, mute) bias cv2 v cc cv3 nc cv4 gnd cv5 nc cvout2 nc cvout3 nc yout nc cout nc cv1 synctc sda scl adr nc cvout1 y1 nc c1 s1 y2 s2 c2 nc c2 2.2 y2 2.2 c1 2.2 y1 2.2 cv1 68k v adr 0.1 i 2 c bus i/o 17 18 19 20 21 22 23 24 cv2 2.2 v cc 9v cv3 2.2 cv4 2.2 cv5 2.2 33 0.01 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 1 26 27 28 29 30 31 32 25 2.2 * 1 unless otherwise specified in the measurement conditions column of electrical characteristics, all are gnd. * 2 unless otherwise specified in the measurement conditions column of electrical characteristics, the supply voltages are as follows. v cc = 9v v adr = 0v when operated with a slave address of 90h. v adr = 9v (v cc ) when operated with a slave address of 92h.
?15 CXA2040Q i 2 c bus control map 1) control register the CXA2040Q control system is comprised of 4 bytes of control registers which control the various outputs. the inputs which are to be output are selected by writing the respective input data into the control register. s: start condition a: acknowledge p: stop condition slave address video switch control map data1 controls the video output 1. data2 controls the video output 2. data3 controls the video output 3. data4 controls the s terminal output. s slave address a data1 a data2 a data3 a data4 a p 100100x0 r/w bit this bit is set to "0" when data is to be written into the control registers. value set by the address pin bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 x x video select x x x bit5 bit4 bit3 other conditions: mute selected input signal 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 mute cv1/yc1 cv2/yc2 cv3 cv4 cv5 cv6 cv7 each register is set to "0" upon power on.
?16 CXA2040Q 2) status register s: start condition p: stop condition a: acknowledge slave address data (1) ponres returns "1" when the CXA2040Q is power on reset. becomes "0" after reading once. (2) syncsep "1" returns if sync exists, "0" if sync does not exist. (3) open/sel for s1 and s2 is determined by comparing the dc voltages for s1 and s2 pins with two threshold levels. s slave address a data na p bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pon res x sync sep x s1 open s1 sel s2 open s2 sel dc voltages for s1 and s2 pins s1, s2 open s1, s2 sel 2v or less 4.75 to 7.25v 9.5 to 12v 0 0 1 1 0 0 100100x1 r/w bit this bit is set to "1" when data is to be read into the status registers. value set by the address pin 3) power on reset the CXA2040Q incorporates a power on reset function which sets each control register to "0" upon power on. (which goes to mute status.) the power on reset v th has hysteresis. the power on v cc and released v cc are as shown below. also, the ponres bit of the status register is read to determine whether the ic is reset upon power on. power on reset release power on reset 4.7v 5.9v vcc
?17 CXA2040Q description of operation 1) composite video system i/os there are three systems of composite outputs. each output switch can select the eight systems of cv1 to cv5 composite video inputs, cv6 and cv7 y/c mix (composite video) inputs and mute. all composite video inputs are input from the input pins to each switch by dc coupling. cv6 is the composite video signal obtained by inputting y1 and c1 to an adder and adding y1 and c1. cv7 is the composite video signal obtained by inputting y2 and c2 to an adder and adding y2 and c2. the cv6 and cv7 composite video signals are input from the input pins to each switch by dc coupling. when mute is selected, the internal bias dc output (approximately v cc /2 [v]) is input to each switch. only one type of input is selected by the i 2 c bus control register. the cvout1 and cvout3 switches output the signal selected by the i 2 c bus at a gain of 0 [db] with respect to the input signal. the switch output stages are push-pull circuits which output at low impedance. the cvout2 switch outputs the signal selected by the i 2 c bus amplified to +6 [db] with respect to the input signal. the switch output stage is a push-pull circuit which outputs at low impedance. the switches are dc coupled from input to output. 2) y system i/os the yout switch can select the three systems of y1, y2 and mute. y1 and y2 are input from the input pins to the switch by dc coupling. when mute is selected, the internal bias dc output (approximately v cc /2 [v]) is input to the switch. only one type of input is selected by the i 2 c bus control register. the yout switch outputs the signal selected by the i 2 c bus at a gain of 0 [db] with respect to the input signal. the switch output stage is a push-pull circuit which outputs at low impedance. the switch is dc coupled from input to output. 3) c system i/os the cout switch can select the three systems of c1, c2 and mute. c1 and c2 are input from the input pins to the switch by dc coupling. when mute is selected, the internal bias dc output (approximately v cc /2 [v]) is input to the switch. only one type of input is selected by the i 2 c bus control register. the cout switch outputs the signal selected by the i 2 c bus at a gain of 0 [db] with respect to the input signal. the switch output stage is a push-pull circuit which outputs at low impedance. the switch is dc coupled from input to output.
?18 CXA2040Q 4) sync discrimination input signal 2.2 23 22 cv1 ic vcc 0.1 68k synctc sync tip clamp and comparator duty discrimination i 2 c fig. 1. sync discrimination circuit block diagram fig. 1 shows the block diagram for the sync discrimination circuit. the signal input from pin 23 (cv1) is sync tip clamped by the external element attached to pin 22. this signal is compared with a threshold voltage which is larger than the sync tip level. if the signal is smaller than the threshold level, it does not proceed to the following stage. at this time, the ic determines that sync does not exist. if the signal is larger than the threshold level, it proceeds to the duty discrimination block. if the duty is greater than 91%, the duty discrimination block determines that sync exists and sends the data to the i 2 c. if the duty is less than 84%, sync is determined not to exist and the data is sent to the i 2 c. the duty discrimination block also has a time constant. after sync is determined to exist, the sync status is held for approximately 14h (ntsc signal) even if the ic goes to a status where sync does not exist such as no signal, etc. if there is no signal or sync does not exist for longer than 14h, the status switches from sync exists to sync does not exist.
?19 CXA2040Q application circuit bias cv2 v cc cv3 nc cv4 gnd cv5 nc cvout2 nc cvout3 nc yout nc cout nc cv1 synctc sda scl adr nc cvout1 y1 nc c1 s1 y2 s2 c2 nc 2.2 v adr i 2 c bus 33 0.01 9 10 11 12 13 14 15 16 CXA2040Q 220 75 luminance signal input 1 2.2 220 chrominance signal input 1 vs 1 2.2 220 luminance signal input 2 vs 2 2.2 220 chrominance signal input 2 2 3 4 5 6 7 8 1 75 75 75 0.47 10 10 10 chrominance signal output luminance signal output composite video signal 0db output 3 composite video signal +6db output 2 composite video signal 0db output 1 10 220 220 0.1 68k 17 18 19 20 21 22 23 24 220 2.2 75 220 2.2 75 0.01 33 vcc 9v 220 2.2 75 220 2.2 75 220 2.2 75 26 30 32 28 27 29 31 25 composite video signal inputs v cc * 1 input pins of pins 1, 3, 5, 7, 23, 25, 27, 29 and 31 are biased to approximately 4.2 to 4.7v. therefore, care should be taken for the capacitance polarity. * 2 output pins of pins 9, 11, 13, 15 and 17 are biased to approximately 3.8 to 4.8v. therefore, care should be taken for the capacitance polarity. * 3 set v adr to 0v (gnd) when the ic slave address is 90h, or to 9v (v cc ) when the ic slave address is 92h. application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?20 CXA2040Q notes on operation connect the power supply side of the by-pass capacitor between the power supply and gnd as close to the pin as possible. take care not to allow interference signals to enter pin 32 (bias). if interference signals enter pin 32, the signal s/n, cross talk and mute will deteriorate. therefore, connect the by-pass capacitor, etc. as close to the pins as possible. for dual surface boards, using one side as a solid earth is best. pins 2, 8, 10, 12, 14, 16, 18, 24 and 28 are nc (not connected) pins. connect these nc pins to gnd. if these nc pins are not connected to gnd, the cross talk and other desired values indicated in the electrical characteristics cannot be obtained. input pins of pins 1, 3, 5, 7, 23, 25, 27, 29 and 31 are biased to approximately 4.2 to 4.7v. therefore, care should be taken for the capacitance polarity. output pins of pins 9, 11, 13, 15 and 17 are biased to approximately 3.8 to 4.8v. therefore, care should be taken for the capacitance polarity.
?21 CXA2040Q curve data 0.1 1 10 ? ? ? ? 0 2 video i/o gain [db] frequency [mhz] cv1 to 5 inputs ? cvout1, 3 frequency response 0.1 1 10 ? 0 2 4 6 8 video i/o gain [db] frequency [mhz] cv1 to 5 inputs ? cvout2 frequency response 0.1 1 10 ? ? ? ? 0 2 video i/o gain [db] frequency [mhz] y/c mix input cvout1, 3 frequency response 0.1 1 10 ? 0 2 4 6 8 video i/o gain [db] frequency [mhz] y/c mix input cvout2 frequency response 0.1 1 10 ? ? ? ? 0 2 video i/o gain [db] frequency [mhz] y input ?yout frequency response 0.1 1 10 ? ? ? ? 0 2 video i/o gain [db] frequency [mhz] c input ?cout frequency response
?22 CXA2040Q package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating 42 alloy 32pin qfp (plastic) 9.0 0.2 7.0 ?0.1 1.5 ?0.15 (8.0) 0.1 ?0.1 + 0.2 + 0.35 + 0.3 0.50 0.127 ?0.05 + 0.1 0?to 10 0.8 0.3 ?0.1 + 0.15 1 8 9 32 16 17 24 25 m 0.12 0.1 0.2g qfp-32p-l01 * qfp032-p-0707-a

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